The present invention relates generally to a method and system for computer aided design (CAD) of integrated circuits (IC) and in particular to layout generation of analog circuits by preserving routing used in a reference layout.
The layout of an IC is stored as data in a computer memory while the IC is designed and transformed to lithography masks used in the printing of semiconductor wafers during the IC manufacturing process. Analog IC electrical characteristics are particularly sensitive to the placement of circuit blocks and traces in the layout. CAD techniques are used by designers extensively in the design and verification of the layout. CAD techniques are also used to keep pace with semiconductor process changes over time that use smaller dimensions to drive better performance at a smaller technology node, which requires changing and verifying the layout according to new design constraints. Fabless companies must also deal with different design constraints even at the same technology node when moving an IC design from one semiconductor fab to another. Automated placement of circuit blocks and the routing of interconnect paths between blocks reduces the engineering cost of migrating an existing design to a new technology node or to a different fab.
Analog IC electrical characteristics are particularly sensitive to the placement of circuit blocks and traces in the layout. Therefore, automated layout generation for analog circuits in advanced technologies is challenging. For decades, to ease the impact from process variation at the transistor level and to ensure high electrical performance, analog layout design has mostly relied on designers' expertise. However, iterative refinement on manual design lengthens the design cycle time on analog layout. Yet, layout design in advanced technology nodes requires consideration of more constraints making the reuse of existing designs more valuable instead of generating new designs from the beginning. Thus, reusable layout template preservation becomes advantageous.
To preserve the design knowledge from an analog template layout, a devices' relative position and routing behaviors should be considered carefully. Typical analog constraints such as symmetry and proximity constraints fundamentally regulate the analog placement. On the other hand, wire symmetry and topological matching are critical to analog routing. Placement and routing from the template layout can be preserved via extraction. The more information extracted from template layout, more likely it preserves the circuit characteristics. Currently, analog layout preservation pays more attention on placement for topology extraction. However, path or wire or net routing behavior extraction is seldom addressed in previous works. Thus there is a need for a methodology to preserve the correlation among existing placement and routing for quick layout generation.
The problem of layout reuse considering analog constraints can be grouped into two stages, placement and routing. At the placement stage, certain approaches mainly focus on compaction and symmetry island generation. Since compaction retains almost the same topology from the source layout, it constructs a symbolic structure to preserve layout topology, technology rules, symmetry and proximity constraints. One solution efficiently provides prototypes with another algorithm in migrated layouts due to the difference scale ratio among devices and reduces the white space under target technology and obtains better performance after post-layout simulation. With symmetry island generation, symmetry pairs are treated as symmetry island and reduce the sensitivity of thermal gradients and process variations. One solution demonstrates hierarchical slicing-tree representation considering monotonic current paths. In addition, a routability-driven analog placement is proposed in another solution.
For routing, existing research focuses on resolving routing with constraints. Early works propose a maze-style router considering symmetry and non-symmetry modules in the same design. Some solutions adopt a channel router to deal with mirror symmetry and detailed routing among blocks. In one solution, matching topology other than the symmetry issue is addressed in placement stage and routing methodology. One solution first defines three typical matching constraints for analog routing which impacts performance most: i) symmetry, ii) topology-matching, and iii) length-matching. In another solution it is proposed that routing priority considering constraint groups in hierarchy can enhance the signal integrity.
Overall, although the symmetry and matching constraints are treated and routing matching constraints are extended further, the correlation among wiring and placement has not been systematically considered. Thus, there is a need for a better way to generate new layout of analog circuits to preserve electrical characteristics of a reference or source design layout by systematically correlating wiring and block placement.